The present disclosure relates to a clock generation circuit and an electronic apparatus, and particularly to a clock generation circuit and electronic apparatus that reduce jitter.
In the past, a clock generation circuit has been used to generate clock signals having various frequencies in an electronic apparatus. For example, a clock generation apparatus including a numerically controlled oscillator, a rounding module, a delay-locked loop (DLL), a multiplexer, and a flip-flop is proposed (see, for example, Japanese Patent Application Laid-open No. 2013-005050). The numerically controlled oscillator in the clock generation apparatus generates a clock signal NCOCLK based on a control signal that controls a phase.
Moreover, the DLL generate M (M represents an integer of 2 or more) clock signals DCLK having different phases by delaying a clock signal MCLK with a plurality of stages of delay elements. Moreover, the rounding module performs rounding calculation in which the value of control signal is rounded into an integer of 0 to M−1 (in other words, quantization). The multiplexer selects any one of the M clock signals DCLK in accordance with the control signal quantized into 0 to M−1. The flip-flop outputs a clock signal OUTCLK in synchronization with the selected clock signal DCLK (in other words, by retiming). Accordingly, the phase of the clock signal OUTCLK can be controlled by the phase resolution depending on the number M of clock signals DCLK.